Given that the number of pins on a processor’s packaging has increased more slowly than the speed of processor performance, off-chip bandwidth has become a critical obstacle to achieving high performance in large systems. A component involved in bridging clock domains is the asynchronous buffer. In this project, we designed an asynchronous buffer to study how a component accepting two different clocks performs and consumes power. The primary goals of this project were to create a fully functional, synthesizable Verilog design of an asynchronous FIFO and simulate it to determine functionality and power consumption in state-of-the-art 32nm CMOS component libraries. Our results provide specific analysis of how dynamic power, static power, throughput, and latency change under different read frequencies, write frequencies, and system loads.